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Disambiguation of "Liu, Ren-Shuo"

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A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

, , , , , , , , , , , , , , , , and . ISSCC, page 494-496. IEEE, (2018)

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Shuo Liu

Shuo Li

Shuo Wang

Shuo Bai

Shuo Zhang

 

Other publications of authors with the same name

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array., , , , , , , , , and 2 other author(s). BioCAS, page 1-4. IEEE, (2018)Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators., , and . ASP-DAC, page 242-247. ACM, (2021)Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference., and . DAC, page 1-6. IEEE, (2023)Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture., and . DAC, page 1-6. IEEE, (2023)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 59 (7): 2297-2309 (July 2024)Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference., , and . ICLR, OpenReview.net, (2023)DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout., , , , and . VLSI-DAT, page 1-4. IEEE, (2018)Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory., , , , and . DATE, page 1-6. IEEE, (2023)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)