Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

W. Chen, K. Li, W. Lin, K. Hsu, P. Li, C. Yang, C. Xue, E. Yang, Y. Chen, Y. Chang, T. Hsu, Y. King, C. Lin, R. Liu, C. Hsieh, K. Tang, and M. Chang. ISSCC, page 494-496. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ya Zhang

Erika Chin

Elion Chin

Ya Yang

Chin Buranadham

Other publications of authors with the same name

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.M. Chang, C. Wu, C. Kuo, S. Shen, K. Lin, S. Yang, Y. King, C. Lin, and Y. Chih. ISSCC, page 434-436. IEEE, (2012)High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications.Y. Huang, Y. Hsieh, Y. Lin, Y. Chih, E. Wang, J. Chang, Y. King, and C. Lin. VLSI Technology and Circuits, page 1-2. IEEE, (2023)A novel single poly-silicon EEPROM using trench floating gate.M. Wu, S. Feng, and Y. King. MTDT, page 35-37. IEEE Computer Society, (2005)An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.M. Chang, S. Shen, C. Liu, C. Wu, Y. Lin, S. Wu, C. Huang, H. Lai, Y. King, C. Lin and 3 other author(s). ISSCC, page 206-208. IEEE, (2011)A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips.M. Chang, C. Wu, J. Hung, Y. King, C. Lin, M. Ho, C. Kuo, and S. Sheu. APCCAS, page 695-698. IEEE, (2014)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.W. Chen, K. Li, W. Lin, K. Hsu, P. Li, C. Yang, C. Xue, E. Yang, Y. Chen, Y. Chang and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.C. Xue, W. Chen, J. Liu, J. Li, W. Lin, W. Lin, J. Wang, W. Wei, T. Chang, T. Chang and 12 other author(s). ISSCC, page 388-390. IEEE, (2019)FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems.Y. Chiang, W. Chien, Y. Chih, J. Chang, C. Lin, and Y. King. Integr., (2019)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.Z. Wang, Y. Liu, A. Lee, F. Su, C. Lo, Z. Yuan, J. Li, C. Lin, W. Chen, H. Chiu and 7 other author(s). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors.A. Lee, C. Lo, C. Lin, W. Chen, K. Hsu, Z. Wang, F. Su, Z. Yuan, Q. Wei, Y. King and 8 other author(s). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)

BibSonomy

Disambiguation of "King, Ya-Chin"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

Please choose a person to relate this publication to

Ya Zhang

Erika Chin

Elion Chin

Ya Yang

Chin Buranadham

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "King, Ya-Chin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.

Please choose a person to relate this publication to

Ya Zhang

Erika Chin

Elion Chin

Ya Yang

Chin Buranadham

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors.