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An Implementation of the System on Chip Control System for a FPGA-Based Computer Vision Accelerator.

, , and . ISOCC, page 299-300. IEEE, (2019)

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Implementation of a Round Robin Processing Element for Deep Learning Accelerator., , , and . ISOCC, page 302-303. IEEE, (2020)Hardware implementation of fast traffic sign recognition for intelligent vehicle system., , , and . ISOCC, page 161-162. IEEE, (2016)Various Threat Models to Circumvent Air-Gapped Systems for Preventing Network Attack., , and . WISA, volume 9503 of Lecture Notes in Computer Science, page 187-199. Springer, (2015)Memory-Centric Architecture of Neural Processing Unit for Edge Device., , , , and . ISOCC, page 240-241. IEEE, (2021)Lightweight and Energy-Efficient Deep Learning Accelerator for Real-Time Object Detection on Edge Devices., , , , and . Sensors, 23 (3): 1185 (February 2023)FPGA Design and Implementation of Accelerated Stereo Matching for Obstacle Detection., , , , and . ICEIC, page 1-2. IEEE, (2019)An Efficient NPU-Aware Filter Pruning in Convolutional Neural Network., , , , and . ICEIC, page 1-3. IEEE, (2023)Exploring GEMM Operations on Different Configurations of the Gemmini Accelerator., , , , and . ISOCC, page 356-357. IEEE, (2022)A Max Pooling Hardware Architecture Supporting Inference And Training For CNN Accelerators., , , , , and . ISOCC, page 313-314. IEEE, (2023)System Level Power Reduction for YOLO2 Sub-modules for Object Detection of Future Autonomous Vehicles., , , , , and . ISOCC, page 151-155. IEEE, (2018)