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Disambiguation of "Unsal, Osman S."

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Hybrid Transactional Memory with Pessimistic Concurrency Control.

, , , , , , , and . Int. J. Parallel Program., 39 (3): 375-396 (2011)

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Osman M s rl

Merâl Ünsal

Ünsal Pul

Tülin Ünsal

Feyzan Ünsal

 

Other publications of authors with the same name

Improving the energy efficiency of hardware-assisted watchpoint systems., , , , and . DAC, page 54:1-54:6. ACM, (2013)System-level power estimation tool for embedded processor based platforms., , , , , and . RAPIDO, page 5:1-5:8. ACM, (2014)PaRV: Parallelizing Runtime Detection and Prevention of Concurrency Errors., , , , and . RV, volume 7687 of Lecture Notes in Computer Science, page 42-47. Springer, (2012)The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment., , , , , , and . Conf. Computing Frontiers, page 67-78. ACM, (2008)Hardware Transactional Memory with Operating System Support, HTMOS., , , and . Euro-Par Workshops, volume 4854 of Lecture Notes in Computer Science, page 8-17. Springer, (2007)VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms., , , , and . PATMOS, page 1-8. IEEE, (2014)Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)Architectural support for efficient message passing on shared memory multi-cores., , , and . J. Parallel Distributed Comput., (2016)Approximating a Multi-Grid Solver., , , and . PMBS@SC, page 97-107. IEEE, (2018)Power and Accuracy of Multi-Layer Perceptrons (MLPs) under Reduced-voltage FPGA BRAMs Operation., , and . CoRR, (2020)