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b$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.

H. Mori, W. Zhao, C. Lee, C. Lee, Y. Hsu, C. Chuang, T. Hashizume, H. Tung, Y. Liu, S. Wu, K. Akarvardar, T. Chou, H. Fujiwara, Y. Wang, Y. Chih, Y. Chen, H. Liao, and T. Chang. ISSCC, page 132-133. IEEE, (2023)

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Yu Hao

Hao Yu

Hsiang-Hao Hsu

Yü-hsiu Hsü

Other publications of authors with the same name

A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology.Y. Hsu, M. Lu, P. Yang, F. Chen, Y. Li, M. Kao, C. Lin, C. Chiu, J. Wu, S. Hsu and 1 other author(s). ISCAS, page 3086-3089. IEEE, (2008)15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.M. Haraguchi, Y. Fujino, Y. Yokoyama, M. Chang, Y. Hsu, H. Cheng, K. Nii, Y. Wang, and T. Chang. ISSCC, page 280-282. IEEE, (2024)A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.Y. Aoyagi, M. Yabuuchi, T. Tanaka, Y. Ishii, Y. Osada, T. Nakazato, K. Nii, I. Wang, Y. Hsu, H. Cheng and 2 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Interpreting Latent Representation in Neural Radiance Fields for Manipulating Object Semantics.Y. Huang, S. Huang, H. Hsu, and Y. Wang. ICIP, page 470-474. IEEE, (2023)SPoVT: Semantic-Prototype Variational Transformer for Dense Point Cloud Semantic Completion.S. Huang, H. Hsu, and Y. Wang. NeurIPS, (2022)Preventing Misuse of Duplicate Certificates in IoT/M2M Systems.Y. Hsu, and F. Lin. ICCCN, page 1-8. IEEE, (2017)A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit.F. Chen, M. Kao, Y. Hsu, C. Lin, J. Wu, C. Chiu, and S. Hsu. ISCAS, page 185-188. IEEE, (2011)A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology.Y. Hsu, Y. Lin, C. Chiu, J. Wu, S. Hsu, F. Chen, M. Kao, and Y. Hsu. ISCAS, page 581-584. IEEE, (2010)A Dynamic Frame Sizing Algorithm for CICQ Switches with 100% Throughput.C. Chang, Y. Hsu, J. Cheng, and D. Lee. INFOCOM, page 747-755. IEEE, (2009)NeurMiPs: Neural Mixture of Planar Experts for View Synthesis.Z. Lin, W. Ma, H. Hsu, Y. Wang, and S. Wang. CVPR, page 15681-15691. IEEE, (2022)

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Disambiguation of "Hsu, Yu-Hao"

Please choose a person to relate this publication to

Yu Hao

Hao Yu

Hao Yu

Hsiang-Hao Hsu

Yü-hsiu Hsü

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hsu, Yu-Hao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 4nm 6163-TOPS/W/b $4790-TOPS/mm^2/b$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.

Please choose a person to relate this publication to

Yu Hao

Hao Yu

Hao Yu

Hsiang-Hao Hsu

Yü-hsiu Hsü

Other publications of authors with the same name

Disambiguation