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Другие публикации лиц с тем же именем

Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique., , , и . VLSI Design, стр. 179-184. IEEE Computer Society, (1997)A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications., , , , , , , , и . VLSI Technology and Circuits, стр. 24-25. IEEE, (2022)Estimation of sequential circuit activity considering spatial and temporal correlations., и . ICCD, стр. 577-582. IEEE Computer Society, (1995)A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity., , , , , , , , , и 8 other автор(ы). ISSCC, стр. 494-495. IEEE, (2023)34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell., , , , , , , , , и 13 other автор(ы). ISSCC, стр. 572-574. IEEE, (2024)Statistical estimation of sequential circuit activity., и . ICCAD, стр. 34-37. IEEE Computer Society / ACM, (1995)Estimation of circuit activity considering signal correlations and simultaneous switching., , и . ICCAD, стр. 300-303. IEEE Computer Society / ACM, (1994)A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations., , , , , , , , , и 8 other автор(ы). ISSCC, стр. 1-3. IEEE, (2022)Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion., , , и . ISPD, стр. 33-38. ACM, (2000)An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 252-254. IEEE, (2021)