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Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing., , , и . Int. J. Netw. Comput., 7 (2): 154-172 (2017)A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems., , , , и . A-SSCC, стр. 1-3. IEEE, (2021)Dynamical Perception-Action Loop Formation with Developmental Embodiment for Hierarchical Active Inference., , , , , и . IWAI, том 1915 из Communications in Computer and Information Science, стр. 14-28. Springer, (2023)Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution., , , , , и . Int. J. Netw. Comput., 6 (2): 195-211 (2016)Spatial computing architecture using randomness of memory cell stability under voltage control., , , и . ECCTD, стр. 1-4. IEEE, (2013)Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers., , и . candar, стр. 196-202. IEEE, (2023)4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems., , , , , , , и . ISSCC, стр. 64-66. IEEE, (2021)24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing., , , , , и . ISSCC, стр. 1-3. IEEE, (2015)Computing architecture to perform approximated simulated annealing for Ising models., , , и . ICRC, стр. 1-8. IEEE Computer Society, (2016)Response Style Characterization for Repeated Measures Using the Visual Analogue Scale., , , , , и . CoRR, (2024)