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Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout.

, , , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (12): 4876-4888 (2021)

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Applications of solid-state memristors in tunable filters., , , , and . ISCAS, page 2269-2272. IEEE, (2014)FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter., , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (1): 103-115 (January 2024)The Design of a Resistive Switching Characterisation Platform Based on Discrete Current-Conveyors., , , and . MOCAST, page 1-4. IEEE, (2023)Design of a Multi-State Memristive Memory., , , , and . ICECS, page 1-6. IEEE, (2021)A high-speed four-channel integrated optical receiver array using SiGe HBT technology., , and . ISCAS, page 433-436. IEEE, (2000)A Wide Dynamic Range Read-out System For Resistive Switching Technology., , , , , and . ISCAS, page 2003-2007. IEEE, (2022)Analogue Circuits Real-Time Emulation based on Wave Digital Filter., , , , and . ISCAS, page 1566-1569. IEEE, (2022)A memristor-CMOS hybrid architecture concept for on-line template matching., , and . ISCAS, page 1-4. IEEE, (2017)Qualitative SPICE modeling accounting for volatile dynamics of TiO2 memristors., , , and . ISCAS, page 2033-2036. IEEE, (2014)A Low Power 10-Bit Time-to-Digital Converter Utilizing Vernier Delay Lines., and . UKSim, page 774-779. IEEE, (2013)