( en | de | ru )

 

Disambiguation of "Maheshwari, Sachin"

Author of the publication

copydeleteadd this publication to your clipboard
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout.

, , , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (12): 4876-4888 (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sachin Arora

Maheshwari Prasad

Sachin Deshmukh

Umesh Maheshwari

Sachin Kinge

 

Other publications of authors with the same name

Logical effort based power-delay-product optimization., , , and . ICACCI, page 565-569. IEEE, (2014)Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers., , and . ECCTD, page 1-4. IEEE, (2017)A Memristor-based Tuneable Offset Comparator., , , and . NEWCAS, page 1-5. IEEE, (2023)Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout., , , , , , , , , and 1 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (12): 4876-4888 (2021)Optimisation of multiperformance characteristics in electric discharge machining of Aluminium Matrix Composites (AMCs) using Taguchi DOE methodology., , and . IJMR, 2 (2): 138-161 (2007)Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology., , , and . VDAT, volume 382 of Communications in Computer and Information Science, page 185-193. Springer, (2013)Characterization of Logical Effort for Improved Delay., , and . VDAT, volume 382 of Communications in Computer and Information Science, page 108-117. Springer, (2013)Impact of Adiabatic Logic Families on the Power-Clock Generator Energy Efficiency., and . PRIME, page 25-28. IEEE, (2019)A CMOS-based Characterisation Platform for Emerging RRAM Technologies., , , , , , , , , and 4 other author(s). ISCAS, page 75-79. IEEE, (2022)An Adiabatic Regenerative Capacitive Artificial Neuron., , , and . ISCAS, page 1-5. IEEE, (2021)