( en | de | ru )

 

Disambiguation of "Wei, Shaojun"

Author of the publication

copydeleteadd this publication to your clipboard
RNA: a reconfigurable architecture for hardware neural acceleration.

, , , , and . DATE, page 695-700. ACM, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

 

Other publications of authors with the same name

Memory fartitioning-based modulo scheduling for high-level synthesis., , , , , and . ISCAS, page 1-4. IEEE, (2017)Reconfigurable computing - evolution of Von Neumann architecture.. FPT, IEEE, (2010)A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration., , , , and . Computer Architecture Letters, 15 (2): 69-72 (2016)Polyhedral model based mapping optimization of loop nests for CGRAs., , , and . DAC, page 19:1-19:8. ACM, (2013)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays., , , and . DAC, page 64:1-64:6. ACM, (2016)Affine transformations for communication and reconfiguration optimization of loops on CGRAs., , , and . ISCAS, page 2541-2544. IEEE, (2013)A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems., , , , , and . A-SSCC, page 191-194. IEEE, (2018)AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs., , , , , , , , , and . NVMSA, page 1-6. IEEE, (2017)Energy-aware loops mapping on multi-vdd CGRAs without performance degradation., , , and . ASP-DAC, page 312-317. IEEE, (2017)LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA., , , , , and . DAC, page 16:1-16:6. ACM, (2018)