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Disambiguation of "Giraud, Bastien"

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An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper.

, , , , , , , and . SLIP, page 4:1-4:7. ACM, (2022)

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Volker Giraud

Reinhard Giraud

Bastien Clausse

Bastien Pietropaoli

Xavier Giraud

 

Other publications of authors with the same name

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs., , , , , , , , , and 10 other author(s). DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures., , , , and . NANOARCH, page 7-12. ACM, (2016)Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro., , , , , , , , , and 9 other author(s). IMW, page 1-4. IEEE, (2023)High density emerging resistive memories: What are the limits?, , , , and . LASCAS, page 1-4. IEEE, (2017)Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities., , and . DATE, page 298-301. IEEE, (2020)Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces., , , , and . DATE, page 1634-1639. IEEE, (2018)Storage Class Memory with Computing Row Buffer: A Design Space Exploration., , , , , , , , , and . DATE, page 1-6. IEEE, (2021)A Dataset Generation Toolbox for Dynamic Security Assessment: On the Role of the Security Boundary., , , , and . CoRR, (January 2025)A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM., , , , , , and . VLSI-SoC, page 1-6. IEEE, (2024)A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology., and . ISCAS, page 1906-1909. IEEE, (2008)