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An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper.

A. Philippe, L. Ciampolini, A. Philippe, M. Gerbaud, M. Ramirez-Corrales, V. Egloff, B. Giraud, and J. Noël. SLIP, page 4:1-4:7. ACM, (2022)

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Reinhard Giraud

Volker Giraud

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Xavier Giraud

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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.E. Beigné, A. Valentian, B. Giraud, O. Thomas, T. Benoist, Y. Thonnart, S. Bernard, G. Moritz, O. Billoint, Y. Maneglia and 10 other author(s). DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures.A. Levisse, B. Giraud, J. Noel, M. Moreau, and J. Portal. NANOARCH, page 7-12. ACM, (2016)High density emerging resistive memories: What are the limits?A. Levisse, B. Giraud, J. Noël, M. Moreau, and J. Portal. LASCAS, page 1-4. IEEE, (2017)Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces.M. Kooli, H. Charles, C. Touzet, B. Giraud, and J. Noel. DATE, page 1634-1639. IEEE, (2018)Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities.V. Gherman, S. Evain, and B. Giraud. DATE, page 298-301. IEEE, (2020)Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro.B. Giraud, S. Ricavy, Y. Moursy, C. Laffond, I. Sever, V. Gherman, M. Pezzin, F. Lepin, M. Diallo, K. Zenati and 9 other author(s). IMW, page 1-4. IEEE, (2023)Storage Class Memory with Computing Row Buffer: A Design Space Exploration.V. Egloff, J. Noel, M. Kooli, B. Giraud, L. Ciampolini, R. Gauchi, C. Tortolero, E. Guthmuller, M. Moreau, and J. Portal. DATE, page 1-6. IEEE, (2021)A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM.L. Rhetat, J. Noel, B. Giraud, L. Grenouillet, J. Laguerre, C. Marchand, and I. O'Connor. VLSI-SoC, page 1-6. IEEE, (2024)Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology.G. Moritz, B. Giraud, J. Noel, D. Turgis, and A. Grover. ICICDT, page 53-56. IEEE, (2013)Software platform dedicated for in-memory computing circuit evaluation.M. Kooli, H. Charles, C. Touzet, B. Giraud, and J. Noël. RSP, page 43-49. ACM, (2017)

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