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An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper.

, , , , , , , and . SLIP, page 4:1-4:7. ACM, (2022)

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Exploration and conception of computing architectures of type computing in-memory based on emerging non volatile memories. (Exploration et conception d'architectures de calcul de type in-memory à base de mémoires non volatiles émergentes).. Aix-Marseille University, France, (2022)Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization., , , , , , , and . ISLPED, page 121-126. ACM, (2020)An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper., , , , , , , and . SLIP, page 4:1-4:7. ACM, (2022)Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing., , , , , , , and . DATE, page 1187-1192. IEEE, (2020)Modeling Clock Glitch Fault Injection Effects on a RISC-V Microcontroller., , , and . IOLTS, page 1-3. IEEE, (2024)Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution., , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 40:1-40:26 (2022)Storage Class Memory with Computing Row Buffer: A Design Space Exploration., , , , , , , , , and . DATE, page 1-6. IEEE, (2021)Inferred Fault Models for RISC-V and Arm: A Comparative Study., , , and . DFT, page 1-6. IEEE, (2024)