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7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate., , , , , , , , , and 24 other author(s). ISSCC, page 1-3. IEEE, (2015)PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion., , , , , , and . ISCAS, page 1902-1905. IEEE, (2008)A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM., , , , , , , , , and 13 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers., , , , , , , , , and 20 other author(s). ISSCC, page 130-131. IEEE, (2016)256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 52 (1): 210-217 (2017)A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 51 (1): 204-212 (2016)7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate., , , , , , , , , and 35 other author(s). ISSCC, page 138-139. IEEE, (2016)A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface., , , , , , , , , and 39 other author(s). ISSCC, page 216-218. IEEE, (2019)25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM., , , , , , , , , and 24 other author(s). ISSCC, page 346-348. IEEE, (2021)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion., , , , , , , , , and 19 other author(s). ISSCC, page 492-617. IEEE, (2007)