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Disambiguation of "Park, Youn-Sik"

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PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion.

, , , , , , and . ISCAS, page 1902-1905. IEEE, (2008)

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Gab-Sik Park

Choon-Sik Park

Rae Sik Park

Hyun-Sik Park

Tae-Sik Park

 

Other publications of authors with the same name

Self-motion utilization for reducing vibration of a structurally flexible redundant robot manipulator system., and . Robotica, 16 (6): 669-677 (1998)Residual vibration reduction for a flexible structure using a modified input shaping technique., and . Robotica, 20 (5): 553-561 (2002)Sound direction estimation using an artificial ear for robots., , and . Robotics Auton. Syst., 59 (3-4): 208-217 (2011)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM., , , , , , and . DAC, page 91:1-91:6. ACM, (2015)PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion., , , , , , and . ISCAS, page 1902-1905. IEEE, (2008)Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM., , , , , , , , , and 25 other author(s). A-SSCC, page 153-156. IEEE, (2017)Residual Vibration Reduction of Time-Varying Flexible Structures by Input Shaping., and . J. Robotics Mechatronics, 6 (3): 220-229 (1994)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking., , , , , , , , , and 39 other author(s). ISSCC, page 204-206. IEEE, (2018)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)