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Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.

E. Breyer, H. Mulaosmanovic, J. Trommer, T. Melde, S. Dünkel, M. Trentzsch, S. Beyer, T. Mikolajick, and S. Slesazeck. ESSDERC, page 118-121. IEEE, (2019)

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Sven Beyer

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Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications.Y. Raffel, S. Thunder, M. Lederer, R. Olivo, R. Hoffmann, L. Pirro, S. Beyer, T. Chohan, P. Huang, S. De and 3 other author(s). ICICDT, page 8-11. IEEE, (2022)Performance Improvement on HfO2-Based 1T Ferroelectric NVM by Electrical Preconditioning.C. Cagli, L. Perniola, F. Gaillard, S. Dünkel, T. Melde, B. Mueller, M. Trentzsch, S. Wittek, and S. Beyer. IRPS, page 1-4. IEEE, (2019)Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.E. Breyer, H. Mulaosmanovic, J. Trommer, T. Melde, S. Dünkel, M. Trentzsch, S. Beyer, T. Mikolajick, and S. Slesazeck. ESSDERC, page 118-121. IEEE, (2019)Performance and Reliability of Technology Qualified 34 Mb Split-Gate eFLASH Macro in 28 nm HKMG.R. Richter, S. Dünkel, B. Müller, F. Mauersberger, S. Wittek, S. Beyer, J. Böhme, U. Ritter, V. Sessi, Z. Xu and 14 other author(s). IMW, page 1-4. IEEE, (2024)Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate.Z. Zhao, S. Woo, K. Aabrar, S. Kirtania, Z. Jiang, S. Deng, Y. Xiao, H. Mulaosmanovic, S. Dünkel, D. Kleimaier and 15 other author(s). CoRR, (2024)Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window.Z. Jiang, Y. Xiao, S. Chatterjee, H. Mulaosmanovic, S. Dünkel, S. Soss, S. Beyer, R. Joshi, Y. Chauhan, H. Amrouch and 2 other author(s). VLSI Technology and Circuits, page 395-396. IEEE, (2022)Endurance improvements and defect characterization in ferroelectric FETs through interface fluorination.Y. Raffel, R. Olivo, M. Lederer, F. Müller, R. Hoffmann, T. Ali, K. Mertens, L. Pirro, M. Drescher, S. Beyer and 4 other author(s). IMW, page 1-4. IEEE, (2022)Novel embedded single poly floating gate flash demonstrated in 22nm FDSOI technology.T. Melde, M. Trentzsch, S. Dünkel, R. Richter, M. Otto, H. Giesler, F. Weisbuch, N. Weddeler, and S. Beyer. IMW, page 1-4. IEEE, (2021)Charge trapping challenges of CMOS embedded complementary FeFETs.S. Beyer, D. Kleimaier, S. Dünkel, H. Mulaosmanovic, S. Soss, J. Müller, Z. Jiang, K. Ni, T. Mikolajick, and H. Zhou. IMW, page 1-4. IEEE, (2024)Multi-Level Operation of Ferroelectric FET Memory Arrays for Compute-In-Memory Applications.F. Müller, S. De, M. Lederer, R. Hoffmann, R. Olivo, T. Kämpfe, K. Seidel, T. Ali, H. Mulaosmanovic, S. Dünkel and 3 other author(s). IMW, page 1-4. IEEE, (2023)

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Disambiguation of "Beyer, Sven"

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Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.

Please choose a person to relate this publication to

Sven Beyer

Sven Beyer

Sven Beyer

Sven Beyer

Sven Beyer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Beyer, Sven"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.

Please choose a person to relate this publication to

Sven Beyer

Sven Beyer

Sven Beyer

Sven Beyer

Sven Beyer

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.