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Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores.

, , и . ISCAS, стр. 1483-1486. IEEE, (2011)

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Christian Mauro

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Frank Mauroschat

 

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Design issues for bus switch systems in deep sub-micro metric CMOS technologies., , и . Circuits, Signals, and Systems, стр. 112-117. IASTED/ACTA Press, (2005)LCD Design Techniques., , и . Wiley Encyclopedia of Computer Science and Engineering, John Wiley & Sons, Inc., (2008)Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices., , , , , , и . HPCA, стр. 1085-1098. IEEE, (2023)The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes., , , , и . ApplePies, том 512 из Lecture Notes in Electrical Engineering, стр. 89-97. Springer, (2017)Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)., , , и . Microelectron. J., 44 (4): 321-331 (2013)Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators., , , , , , и . ApplePies, том 1036 из Lecture Notes in Electrical Engineering, стр. 149-154. Springer, (2022)BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge., , , , , и . ASPLOS, стр. 56-69. ACM, (2022)A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications., , и . ICCD, стр. 476-481. IEEE Computer Society, (1999)Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems., , , , , и . IEEE Access, (2024)A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection., , , , , и . IEEE Access, (2024)