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Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.

K. Feng, A. Carsello, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak, J. Setter, J. Thomas, K. Sreedhar, P. Chen, N. Bhagdikar, Z. Myers, B. D'Agostino, P. Joshi, S. Richardson, R. Bahr, C. Torng, M. Horowitz, and P. Raina. HCS, page 1-30. IEEE, (2022)

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Liu Liu

Lu Liu

Lei Liu

Other publications of authors with the same name

Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis.X. Chen, Q. Liu, S. Yao, J. Wang, Q. Xu, Y. Wang, Y. Liu, and H. Yang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (7): 1370-1383 (2018)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators.Q. Liu, J. Setter, D. Huff, M. Strange, K. Feng, M. Horowitz, P. Raina, and F. Kjolstad. ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)FASTrust: Feature analysis for third-party IP trust verification.S. Yao, X. Chen, J. Zhang, Q. Liu, J. Wang, Q. Xu, Y. Wang, and H. Yang. ITC, page 1-10. IEEE, (2015)Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.K. Feng, A. Carsello, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). HCS, page 1-30. IEEE, (2022)Creating an Agile Hardware Design Flow.R. Bahr, C. Barrett, N. Bhagdikar, A. Carsello, R. Daly, C. Donovick, D. Durst, K. Fatahalian, K. Feng, P. Hanrahan and 22 other author(s). DAC, page 1-6. IEEE, (2020)Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators.X. Yang, M. Gao, Q. Liu, J. Setter, J. Pu, A. Nayak, S. Bell, K. Cao, H. Ha, P. Raina and 2 other author(s). ASPLOS, page 369-383. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..Compiling Halide Programs to Push-Memory Accelerators.Q. Liu, D. Huff, J. Setter, M. Strange, K. Feng, K. Sreedhar, Z. Wang, K. Zhang, M. Horowitz, P. Raina and 1 other author(s). CoRR, (2021)Low-overhead implementation of logic encryption using gate replacement techniques.X. Chen, Q. Liu, Y. Wang, Q. Xu, and H. Yang. ISQED, page 257-263. IEEE, (2017)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.A. Carsello, K. Feng, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)

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Disambiguation of "Liu, Qiaoyi"

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Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Lu Liu

Lei Liu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Liu, Qiaoyi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Lu Liu

Lei Liu

Other publications of authors with the same name

Disambiguation

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Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.