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An End-to-End HW/SW Co-Design Methodology to Design Efficient Deep Neural Network Systems using Virtual Models.

, , , , , , , и . INTESA, стр. 18-22. ACM, (2019)

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Leonardo Estupiñán

Leonardo Finocchi

Leonardo Ebeling

Leonardo Dude

Leonardo Bianchi

 

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Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators., , и . IPDPS Workshops, стр. 840-843. IEEE, (2020)An End-to-End HW/SW Co-Design Methodology to Design Efficient Deep Neural Network Systems using Virtual Models., , , , , , , и . INTESA, стр. 18-22. ACM, (2019)Architecting high-speed command schedulers for open-row real-time SDRAM controllers., и . DATE, стр. 626-629. IEEE, (2017)Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance., , и . ECRTS, стр. 3-13. IEEE Computer Society, (2016)A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs., , , , , , , и . ASP-DAC, стр. 35-42. ACM, (2021)Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling., и . RTSS, стр. 53-64. IEEE Computer Society, (2015)Adaptive load distribution in mixed-critical Networks-on-Chip., , , и . ASP-DAC, стр. 732-737. IEEE, (2017)Architecture and Performance Analysis of a Multi-Generation SDRAM Controller for Mixed Criticality Systems (Architektur- und Leistungsanalyse eines Mehgenerationen-SDRAM-Controllers für gemischte Kritikalitätssysteme). Braunschweig University of Technology, Germany, (2018)base-search.net (ftunivbraunschw:oai:https://leopard.tu-braunschweig.de/:dbbs_mods_00066059).SPARC16: A New Compression Approach for the SPARC Architecture., , , , , и . SBAC-PAD, стр. 169-176. IEEE Computer Society, (2009)