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Disambiguation of "Olivieri, Mauro"

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Side channel analysis resistant design flow.

, , , , , , , and . ISCAS, IEEE, (2006)

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Christian Mauro

Nicoletta Olivieri

Gillian Olivieri

Lilian Olivieri

Frank Mauroschat

 

Other publications of authors with the same name

Design issues for bus switch systems in deep sub-micro metric CMOS technologies., , and . Circuits, Signals, and Systems, page 112-117. IASTED/ACTA Press, (2005)LCD Design Techniques., , and . Wiley Encyclopedia of Computer Science and Engineering, John Wiley & Sons, Inc., (2008)The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes., , , , and . ApplePies, volume 512 of Lecture Notes in Electrical Engineering, page 89-97. Springer, (2017)Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)., , , and . Microelectron. J., 44 (4): 321-331 (2013)Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices., , , , , , and . HPCA, page 1085-1098. IEEE, (2023)Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators., , , , , , and . ApplePies, volume 1036 of Lecture Notes in Electrical Engineering, page 149-154. Springer, (2022)BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge., , , , , and . ASPLOS, page 56-69. ACM, (2022)A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications., , and . ICCD, page 476-481. IEEE Computer Society, (1999)Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems., , , , , and . IEEE Access, (2024)A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection., , , , , and . IEEE Access, (2024)