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PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators., , , , , , and . VLSI Circuits, page 263-264. IEEE, (2018)A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR., , , , , , , , , and 8 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 443-452 (2013)28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique., , , , , , , , and . ISSCC, page 478-479. IEEE, (2017)PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation., , , , , and . CoRR, (2024)Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections., , , and . IROS, page 1578-1584. IEEE, (2021)A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration., , , and . CICC, page 1-2. IEEE, (2023)An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (2): 356-368 (2015)7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique., , , , and . VLSIC, page 1-2. IEEE, (2014)A voltage scaling 0.25-1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier., , , and . ISCAS, page 809-812. IEEE, (2013)