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Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization.

, , и . ASPLOS, стр. 395-410. ACM, (2019)

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Ashish Shah

Venkat Chandar

Ashish Shrivastava

Ashish Choudhary

Venkat Chandrasekaran

 

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SecSMT: Securing SMT Processors against Contention-Based Covert Channels., , , и . USENIX Security Symposium, стр. 3165-3182. USENIX Association, (2022)Execution migration in a heterogeneous-ISA chip multiprocessor., , и . ASPLOS, стр. 261-272. ACM, (2012)CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities., и . ISCA, стр. 762-775. IEEE, (2020)I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches., , , , , и . ISCA, стр. 361-374. IEEE, (2021)Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching., , , , и . ISCA, стр. 251-264. IEEE, (2021)Agon: A Scalable Competitive Scheduler for Large Heterogeneous Systems., , и . CoRR, (2021)Breaking the ISA Barrier in Modern Computing.. University of California, San Diego, USA, (2018)Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor., и . ISCA, стр. 121-132. IEEE Computer Society, (2014)Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management., , и . IEEE Micro, 39 (3): 75-83 (2019)Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures., , и . PMAM@PPoPP, стр. 51-60. ACM, (2019)