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A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET with -20.3dBm OMA Sensitivity and 691fJ/bit.

, , , , , , , , , , , , , , , и . OFC, стр. 1-3. IEEE, (2023)

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Denis Palermo

Francesco Palermo

Mario Palermo

Christophe Palermo

Samuel Taddese

 

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3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS., , , , , и . ISSCC, стр. 1-3. IEEE, (2015)SEE Sensitivity of a 16GHz LC-Tank VCO in a 22nm FinFET Technology., , , , и . ISCAS, стр. 254-257. IEEE, (2022)Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS., , , и . CICC, стр. 1-4. IEEE, (2011)A 0.18-μm CMOS fully integrated 0.7-6 GHz PLL-based complex dielectric spectroscopy system., , , , и . CICC, стр. 1-4. IEEE, (2014)Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper)., , , и . MWSCAS, стр. 1151-1154. IEEE, (2019)A Wide-Band Fully-Integrated CMOS Ring-Oscillator PLL-Based Complex Dielectric Spectroscopy System., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 1940-1949 (2015)A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications., , , , и . IEEE J. Solid State Circuits, 49 (11): 2560-2574 (2014)A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage., , , , и . IEEE J. Solid State Circuits, 52 (3): 657-668 (2017)A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization., , , , , и . IEEE J. Solid State Circuits, 51 (3): 671-685 (2016)A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS., , , , , , , , , и . IEEE J. Solid State Circuits, 54 (3): 672-684 (2019)