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Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators.

L. Canese, G. Cardarilli, L. Nunzio, R. Fazzolari, M. Re, and S. Spanò. ApplePies, volume 1036 of Lecture Notes in Electrical Engineering, page 242-247. Springer, (2022)

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Gian Carlo Aloardi

Gian Carlo Gullo

Gian-Carlo Sciuchetti

Gian Töndury

Teresa Carlomagno

Other publications of authors with the same name

Digital Signal Processing Accelerator for RISC-V.L. Calicchia, V. Ciotoli, G. Cardarilli, L. Nunzio, R. Fazzolari, A. Nannarelli, and M. Re. ICECS, page 703-706. IEEE, (2019)FPGA realization of RNS to binary signed conversion architecture.M. Re, A. Nannarelli, G. Cardarilli, and R. Lojacono. ISCAS (4), page 350-353. IEEE, (2001)A Wireless Sensor Node Based on Microbial Fuel Cell.S. Acciarito, G. Cardarilli, L. Nunzio, R. Fazzolari, and M. Re. ApplePies, volume 409 of Lecture Notes in Electrical Engineering, page 143-150. Springer, (2015)Compressive sensing spectrum analysis for space autonomous radio receivers.G. Cardarilli, M. Re, I. Shuli, and L. Simone. ACSSC, page 492-494. IEEE, (2013)Power efficient design of parallel/serial FIR filters in RNS.M. Petricca, P. Albicocco, G. Cardarilli, A. Nannarelli, and M. Re. ACSCC, page 1015-1019. IEEE, (2012)IP based reconfigurable digital platform for satellite communications.G. Cardarilli, A. Re, and M. Re. ISCAS (2), page 37-40. IEEE, (2003)Bipolar and CMOS low voltage-supply reduced-power voltage followers.G. Ferri, F. Alfonsetti, G. Cardarilli, and M. Re. ICECS, page 1503-1506. IEEE, (1999)Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.S. Pontarelli, L. Sterpone, G. Cardarilli, M. Re, M. Reorda, A. Salsano, and M. Violante. IOLTS, page 194-196. IEEE Computer Society, (2007)A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture.G. Cardarilli, A. Salsano, P. Marinucci, and M. Ottavi. DFT, page 173-. IEEE Computer Society, (2000)System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology.S. Pontarelli, G. Cardarilli, A. Malvoni, M. Ottavi, M. Re, and A. Salsano. DFT, page 455-460. IEEE Computer Society, (2001)

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Disambiguation of "Cardarilli, Gian Carlo"

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Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators.

Please choose a person to relate this publication to

Gian Carlo Aloardi

Gian Carlo Gullo

Gian-Carlo Sciuchetti

Gian Töndury

Teresa Carlomagno

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cardarilli, Gian Carlo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators.

Please choose a person to relate this publication to

Gian Carlo Aloardi

Gian Carlo Gullo

Gian-Carlo Sciuchetti

Gian Töndury

Teresa Carlomagno

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators.