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A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator., , и . IEEE J. Solid State Circuits, 35 (10): 1453-1460 (2000)All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs., , , и . ISSCC, стр. 176-595. IEEE, (2007)Experimental Analysis of Substrate Noise Effect on PLL Performance., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (7): 638-642 (2008)A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS., , , и . ICTA, стр. 76-77. IEEE, (2021)A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection., , , и . CICC, стр. 1-2. IEEE, (2022)9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications., , , , , и . ISSCC, стр. 160-161. IEEE, (2014)A 17.3mW IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65nm CMOS., , и . ESSCIRC, стр. 53-56. IEEE, (2023)An overview of digital-intensive ΔΣ phase-locked loops utilizing 1-bit conversion and modulation., , , , и . MWSCAS, стр. 1-4. IEEE, (2016)An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution., , и . IEEE J. Solid State Circuits, 37 (4): 515-520 (2002)A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL., , , , , и . CICC, стр. 1-4. IEEE, (2019)