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A Split L2 Data Cache for Scalable Cc-numa Multiprocessors., , and . Journal of Circuits, Systems, and Computers, 14 (3): 605-618 (2005)Is the Complicated ECC Array Necessary for Data Caches?, , , and . CDES, page 137-139. CSREA Press, (2007)Architecture/OS Support for Embedded Multi-core Systems., , and . Comput. J., 53 (8): 1134-1135 (2010)Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay., , and . ISQED, page 524-530. IEEE, (2013)An energy-efficient task scheduler for mobile web browsing., , and . ICCE, page 188-189. IEEE, (2017)Correction to: Aggressive GPU cache bypassing with monolithic 3D-based NoC., , and . J. Supercomput., 79 (6): 7061 (April 2023)An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors., , and . IEEE Trans. Computers, 64 (9): 2460-2475 (2015)A Survey on Recent OS-Level Energy Management Techniques for Mobile Processing Units., , and . IEEE Trans. Parallel Distributed Syst., 29 (10): 2388-2401 (2018)A High-Performance Processing-in-Memory Accelerator for Inline Data Deduplication., , , , and . ICCD, page 515-523. IEEE, (2019)Energy-Effective Instruction Fetch Unit for Embedded Processors., , , , , and . CCNC, page 734-735. IEEE, (2008)