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Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices., , and . VLSID, page 5-6. IEEE Computer Society, (2014)Probe point insertion for at-speed test., , and . VTS, page 223-228. IEEE Computer Society, (1992)Impact of high level functional constraints on testability., , and . VTS, page 309-312. IEEE Computer Society, (1993)Design for Testability Using Architectural Descriptions., , and . ITC, page 752-761. IEEE Computer Society, (1992)A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs., , , , and . ITC, page 1-10. IEEE Computer Society, (2008)A Design For Test Perspective on I/O Management., , , and . ICCD, page 46-53. IEEE Computer Society, (1996)Non-Scan Design-for-Testability Techniques for Sequential Circuits., , , and . DAC, page 236-241. ACM Press, (1993)Advancing test compression to the physical dimension., , , , , , , , and . ITC, page 1-10. IEEE, (2017)A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures., , , , , , and . NATW, page 43-48. IEEE, (2015)A comparative study of design for testability methods using high-level and gate-level descriptions., , and . ICCAD, page 620-624. IEEE Computer Society / ACM, (1992)