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A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures.

S. Chillarige, S. Virdi, A. Malik, K. Chakravadhanula, V. Chickermane, J. Swenton, and G. Vandling. NATW, page 43-48. IEEE, (2015)

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Krishna Saxena

Krishna-K

Krishna Moorthi

Krishna Zivraj

Krishna Narasimhan

Other publications of authors with the same name

Improving Diagnosis Resolution and Performance at High Compression Ratios.S. Chillarige, A. Chhabra, A. Malik, B. Nandakumar, J. Swenton, and K. Chakravadhanula. ITC, page 1-8. IEEE, (2018)Low cost at-speed testing using On-Product Clock Generation compatible with test compression.B. Keller, K. Chakravadhanula, B. Foutz, V. Chickermane, R. Malneedi, T. Snethen, V. Iyengar, D. Lackey, and G. Grise. ITC, page 724-733. IEEE Computer Society, (2010)Advancing test compression to the physical dimension.K. Chakravadhanula, V. Chickermane, P. Cunningham, B. Foutz, D. Meehl, L. Milano, C. Papameletis, D. Scott, and S. Wilcox. ITC, page 1-10. IEEE, (2017)A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures.S. Chillarige, S. Virdi, A. Malik, K. Chakravadhanula, V. Chickermane, J. Swenton, and G. Vandling. NATW, page 43-48. IEEE, (2015)A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs.V. Chickermane, P. Jr., J. Sage, P. Yuan, and K. Chakravadhanula. ITC, page 1-10. IEEE Computer Society, (2008)Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices.S. Ravi, V. Chickermane, and K. Chakravadhanula. VLSID, page 5-6. IEEE Computer Society, (2014)Low Power Reduced Pin Count Test Methodology.K. Chakravadhanula, N. Parimi, B. Foutz, B. Li, and V. Chickermane. ATS, page 251-258. IEEE, (2007)Efficient testing of hierarchical core-based SOCs.B. Keller, K. Chakravadhanula, B. Foutz, V. Chickermane, A. Garg, R. Schoonover, J. Sage, D. Pearl, and T. Snethen. ITC, page 1-10. IEEE Computer Society, (2014)Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?.K. Chakravadhanula, V. Chickermane, B. Keller, P. Jr., and A. Uzzaman. Asian Test Symposium, page 295-300. IEEE Computer Society, (2009)PPA Optimization of Test Points in Automotive Designs.B. Foutz, S. Singhal, P. Rai, K. Chakravadhanula, V. Chickermane, B. Nandakumar, S. Chillarige, C. Papameletis, and S. Ravichandran. ITC, page 204-212. IEEE, (2022)

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Disambiguation of "Chakravadhanula, Krishna"

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A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures.

Please choose a person to relate this publication to

Krishna Saxena

Krishna-K

Krishna Moorthi

Krishna Zivraj

Krishna Narasimhan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chakravadhanula, Krishna"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures.

Please choose a person to relate this publication to

Krishna Saxena

Krishna-K

Krishna Moorthi

Krishna Zivraj

Krishna Narasimhan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures.