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Disambiguation of "Yoshimoto, Shusuke"

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A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems.

, , , , , , , , , , , , , , and . BioCAS, page 280-283. IEEE, (2014)

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Kei Yoshimoto

 

Other publications of authors with the same name

7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2693-2700 (2011)A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique., , , , , , and . ASP-DAC, page 77-78. IEEE, (2013)A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells., , , and . ASP-DAC, page 79-80. IEEE, (2013)A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques., , , , , , , , , and 4 other author(s). ISCAS, page 2904-2907. IEEE, (2015)Noise Evaluation System for Biosignal Sensors Using Pseudo-Skin and Helmholtz Coil., , , , , , , and . ISMICT, page 1-4. IEEE, (2019)A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19., , , and . ESSCIRC, page 527-530. IEEE, (2011)Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy., , , , , , and . CICC, page 1-4. IEEE, (2011)A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems., , , , , , , , , and 5 other author(s). BioCAS, page 280-283. IEEE, (2014)A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction., , , , , , and . ISQED, page 489-492. IEEE, (2012)A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor., , , , , , , , , and . CICC, page 1-4. IEEE, (2015)