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Disambiguation of "Asai, Tetsuya"

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Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation.

, , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (4): 462-466 (2017)

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Kwaichiro Asai

Tetsuya Takahashi

Yusuke Asai

Tetsuya Mizutani

Tetsuya Kawata

 

Other publications of authors with the same name

Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits., , and . ICONIP (1), volume 6443 of Lecture Notes in Computer Science, page 188-195. Springer, (2010)Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers., , , and . ICECS, page 140-143. IEEE, (2009)Silicon neuron design based on phase reduction analysis., , and . SCIS&ISIS, page 1059-1062. IEEE, (2012)On Digital LSI Circuits Exploiting Collision-Based Fusion Gates., , , and . Int. J. Unconv. Comput., 4 (1): 45-59 (2008)Towards reaction-diffusion computing devices based on minority-carrier transport in semiconductors, , and . Chaos, Solitons & Fractals, 20 (4): 863--876 (May 2004)A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology., , , and . SMC, page 6. IEEE, (2002)A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors., , , and . Int. J. Bifurc. Chaos, 17 (5): 1713-1719 (2007)A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs., , , and . IEEE J. Solid State Circuits, 44 (7): 2047-2054 (2009)A subthreshold MOS neuron circuit based on the Volterra system., , and . IEEE Trans. Neural Networks, 14 (5): 1308-1312 (2003)Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata., , , and . IEICE Electron. Express, 1 (9): 248-252 (2004)