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Disambiguation of "Ueyoshi, Kodai"

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Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation.

, , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (4): 462-466 (2017)

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Keiichi Kodaira

 

Other publications of authors with the same name

Exploring optimized accelerator design for binarized convolutional neural networks., , , , , and . IJCNN, page 2510-2516. IEEE, (2017)FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting., , , , , and . ReConFig, page 1-6. IEEE, (2016)Logarithmic Compression for Memory Footprint Reduction in Neural Network Training., , , , , , , , and . CANDAR, page 291-297. IEEE Computer Society, (2017)QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 54 (1): 186-196 (2019)Accelerating deep learning by binarized hardware., , , , , , , and . APSIPA, page 1045-1051. IEEE, (2017)QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS., , , , , , , , and . ISSCC, page 216-218. IEEE, (2018)A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 692-703 (2021)DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2022)A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes., , , , , , , , and . ISCAS, page 1-5. IEEE, (2020)In-memory area-efficient signal streaming processor design for binary neural networks., , , , , , , , , and 1 other author(s). MWSCAS, page 116-119. IEEE, (2017)