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17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.

, , , , , , , , , , , и . ISSCC, стр. 1-3. IEEE, (2015)

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Esther Fujiwara

 

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12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 206-207. IEEE, (2017)A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , и . SoCC, стр. 143-147. IEEE, (2012)A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry., , , , , , и . ISQED, стр. 438-441. IEEE, (2013)A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications., , , , , , , , и . VLSI Technology and Circuits, стр. 24-25. IEEE, (2022)3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications., , , , , , , , и . VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing., , , , , , и . ISVLSI, стр. 107-112. IEEE Computer Society, (2007)34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell., , , , , , , , , и 13 other автор(ы). ISSCC, стр. 572-574. IEEE, (2024)Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application., , , , , и . ISQED, стр. 270-274. IEEE, (2012)A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs., , , , , , , и . ISSCC, стр. 236-238. IEEE, (2012)Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation., , , , , , и . SoCC, стр. 519-524. IEEE, (2010)