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Disambiguation of "Wijeratne, Sasindu"

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Scalable High Performance SDN Switch Architecture on FPGA for Core Networks.

, , , , and . FPGA, page 117. ACM, (2019)

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Other publications of authors with the same name

Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration., , , , and . FPL, page 219-227. IEEE, (2023)Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks., , , and . ASAP, page 1-7. IEEE Computer Society, (2018)Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks., , , and . CoRR, (2021)Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA., , and . HPEC, page 1-7. IEEE, (2021)Modeling the Energy Efficiency of GEMM using Optical Random Access Memory., , , , , , and . HPEC, page 1-7. IEEE, (2022)High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension., , , , , , , , , and 1 other author(s). ASAP, page 164-169. IEEE Computer Society, (2017)Scalable High Performance SDN Switch Architecture on FPGA for Core Networks., , , , and . FPGA, page 117. ACM, (2019)A High Throughput Parallel Hash Table on FPGA using XOR-based Memory., , , , and . HPEC, page 1-7. IEEE, (2020)Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA., , , , and . HPEC, page 1-7. IEEE, (2022)Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA., , , and . FPGA, page 259-269. ACM, (2023)