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Intra- and inter-chip electrical interconnection formed by directed self assembly of nanocomposite containing diblock copolymer and nanometal., , , , and . IRPS, page 4. IEEE, (2018)Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers., , , , , , , , and . 3DIC, page TS1.2.1-TS1.2.4. IEEE, (2015)Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM., , , , , and . IRPS, page 4. IEEE, (2015)Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University., , , , and . 3DIC, page FS2.1-FS2.5. IEEE, (2015)Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration., , , , and . 3DIC, page 1-4. IEEE, (2019)Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration., , , , , , , , and . 3DIC, page 1-5. IEEE, (2009)Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV., , , , , , , and . 3DIC, page 1-4. IEEE, (2014)Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI., , , , , , , and . 3DIC, page 1-4. IEEE, (2014)Heterogeneous integration technology for MEMS-LSI multi-chip module., , , , , , , and . 3DIC, page 1-6. IEEE, (2009)