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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

P. Klim, J. Barth, W. Reohr, D. Dick, G. Fredeman, G. Koch, H. Le, A. Khargonekar, P. Wilcox, J. Golz, J. Kuang, A. Mathews, J. Law, T. Luong, H. Ngo, R. Freese, H. Hunter, E. Nelson, P. Parries, T. Kirihata, and S. Iyer. IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)

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Balasubramaniam Iyer

Preeti Ramesh Iyer

Balasubramaniam Iyer

Chandrasekhar Iyer

Balasubramaniam Iyer

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Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM.D. Fainstein, S. Rosenblatt, A. Cestero, N. Robson, T. Kirihata, and S. Iyer. VLSIC, page 146-147. IEEE, (2012)Integrated neural interfaces.R. Walker, L. Rieth, S. Iyer, A. Bajwa, J. Silver, T. Ahmed, N. Tasneem, M. Sharma, and A. Gardner. MWSCAS, page 1045-1048. IEEE, (2017)45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.S. Iyer, G. Freeman, C. Brodsky, A. Chou, D. Corliss, S. Jain, N. Lustig, V. McGahay, S. Narasimha, J. Norum and 10 other author(s). IBM J. Res. Dev., 55 (3): 5 (2011)A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS.G. Uhlmann, T. Aipperspach, T. Kirihata, K. Chandrasekharan, Y. Li, C. Paone, B. Reed, N. Robson, J. Safran, D. Schmitt and 1 other author(s). ISSCC, page 406-407. IEEE, (2008)A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration.U. Rathore, S. Nagi, S. Iyer, and D. Markovic. ISSCC, page 52-54. IEEE, (2022)A Case for Packageless Processors.S. Pal, D. Petrisko, A. Bajwa, P. Gupta, S. Iyer, and R. Kumar. HPCA, page 466-479. IEEE Computer Society, (2018)Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration.A. Kumar, Z. Wan, W. Wilcke, and S. Iyer. JETC, 13 (3): 45:1-45:21 (2017)Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias.T. Kirihata, J. Golz, M. Wordeman, P. Batra, G. Maier, N. Robson, T. Graves abe, D. Berger, and S. Iyer. IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 373-384 (2016)Designing a 2048-Chiplet, 14336-Core Waferscale Processor.S. Pal, J. Liu, I. Alam, N. Cebry, H. Suhail, S. Bu, S. Iyer, S. Pamarti, R. Kumar, and P. Gupta. DAC, page 1183-1188. IEEE, (2021)An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices.S. Nouri, and S. Iyer. ISSCC, page 434-435. IEEE, (2023)

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Disambiguation of "Iyer, Subramanian S."

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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Please choose a person to relate this publication to

Balasubramaniam Iyer

Preeti Ramesh Iyer

Balasubramaniam Iyer

Chandrasekhar Iyer

Balasubramaniam Iyer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Iyer, Subramanian S."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Please choose a person to relate this publication to

Balasubramaniam Iyer

Preeti Ramesh Iyer

Balasubramaniam Iyer

Chandrasekhar Iyer

Balasubramaniam Iyer

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.