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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

P. Klim, J. Barth, W. Reohr, D. Dick, G. Fredeman, G. Koch, H. Le, A. Khargonekar, P. Wilcox, J. Golz, J. Kuang, A. Mathews, J. Law, T. Luong, H. Ngo, R. Freese, H. Hunter, E. Nelson, P. Parries, T. Kirihata, and S. Iyer. IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)

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William Herz

William Cahill

William Jorns

William Pierson

William Döhrmann

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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.P. Klim, J. Barth, W. Reohr, D. Dick, G. Fredeman, G. Koch, H. Le, A. Khargonekar, P. Wilcox, J. Golz and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.J. Barth, W. Reohr, P. Parries, G. Fredeman, J. Golz, S. Schuster, R. Matick, H. Hunter, C. Tanner, J. Harig and 7 other author(s). ISSCC, page 486-617. IEEE, (2007)An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.J. Kuang, A. Mathews, J. Barth, F. Gebara, T. Nguyen, J. Schaub, K. Nowka, G. Carpenter, D. Plass, E. Nelson and 3 other author(s). ESSCIRC, page 66-69. IEEE, (2008)Memories: Exploiting Them and Developing Them.W. Reohr. SoCC, page 303-310. IEEE, (2006)Design SRAMs for burn-in.W. Reohr, Y. Chan, D. Plass, A. Pelella, and P. Wu. VTS, page 164-170. IEEE Computer Society, (1993)Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications.P. Emma, W. Reohr, and M. Meterelliyoz. IEEE Micro, 28 (6): 47-56 (2008)A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.J. Barth, D. Plass, E. Nelson, C. Hwang, G. Fredeman, M. Sperling, A. Mathews, T. Kirihata, W. Reohr, K. Nair and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)Statistical yield analysis of silicon-on-insulator embedded DRAM.R. Kanj, R. Joshi, J. Kuang, J. Kim, M. Meterelliyoz, W. Reohr, S. Nassif, and K. Nowka. ISQED, page 190-194. IEEE Computer Society, (2009)A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.J. Barth, D. Plass, E. Nelson, C. Hwang, G. Fredeman, M. Sperling, A. Mathews, W. Reohr, K. Nair, and N. Cao. ISSCC, page 342-343. IEEE, (2010)

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Disambiguation of "Reohr, William R."

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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Please choose a person to relate this publication to

William Herz

William Cahill

William Jorns

William Pierson

William Döhrmann

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Reohr, William R."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Please choose a person to relate this publication to

William Herz

William Cahill

William Jorns

William Pierson

William Döhrmann

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.