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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

P. Klim, J. Barth, W. Reohr, D. Dick, G. Fredeman, G. Koch, H. Le, A. Khargonekar, P. Wilcox, J. Golz, J. Kuang, A. Mathews, J. Law, T. Luong, H. Ngo, R. Freese, H. Hunter, E. Nelson, P. Parries, T. Kirihata, and S. Iyer. IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)

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Ngo Hung Manh

Ngo Phuc Hung

Ngo Hung Manh

Other publications of authors with the same name

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.R. Kanj, R. Joshi, Z. Li, J. Kuang, H. Ngo, N. Zhou, W. Shi, and S. Nassif. ISLPED, page 87-92. ACM, (2008)A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.J. Kuang, H. Ngo, K. Nowka, J. Law, and R. Joshi. ICCD, page 574-584. IEEE Computer Society, (2005)Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.J. Sivagnaname, H. Ngo, K. Nowka, R. Montoye, and R. Brown. VLSI Design, page 89-93. IEEE Computer Society, (2006)Design methodology for a 1.0 GHz microprocessor.S. Posluszny, N. Aoki, D. Boerstler, J. Burns, S. Dhong, U. Ghoshal, H. Hofstee, D. LaPotin, K. Lee, D. Meltzer and 5 other author(s). ICCD, page 17-23. IEEE Computer Society, (1998)Controlled-Load Limited Switch Dynamic Logic Circuit.J. Sivagnaname, H. Ngo, K. Nowka, R. Montoye, and R. Brown. ISQED, page 83-87. IEEE Computer Society, (2005)A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling.K. Nowka, G. Carpenter, E. MacDonald, H. Ngo, B. Brock, K. Ishii, T. Nguyen, and J. Burns. IEEE J. Solid State Circuits, 37 (11): 1441-1447 (2002)A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.P. Klim, J. Barth, W. Reohr, D. Dick, G. Fredeman, G. Koch, H. Le, A. Khargonekar, P. Wilcox, J. Golz and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)A low latency and low power dynamic Carry Save Adder.R. Datta, J. Abraham, R. Montoye, W. Belluomini, H. Ngo, C. McDowell, J. Kuang, and K. Nowka. ISCAS (2), page 477-480. IEEE, (2004)

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Disambiguation of "Ngo, Hung C."

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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Please choose a person to relate this publication to

Ngo Hung Manh

Ngo Hung Manh

Ngo Phuc Hung

Ngo Hung Manh

Ngo Hung Manh

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ngo, Hung C."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Please choose a person to relate this publication to

Ngo Hung Manh

Ngo Hung Manh

Ngo Phuc Hung

Ngo Hung Manh

Ngo Hung Manh

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.