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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

P. Klim, J. Barth, W. Reohr, D. Dick, G. Fredeman, G. Koch, H. Le, A. Khargonekar, P. Wilcox, J. Golz, J. Kuang, A. Mathews, J. Law, T. Luong, H. Ngo, R. Freese, H. Hunter, E. Nelson, P. Parries, T. Kirihata, and S. Iyer. IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)

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Julia Hunter

Hunter Rouse

Charles Hunter

Regina Hunter

Aleksandra Hunter

Other publications of authors with the same name

Code coverage and input variability: effects on architecture and compiler research.H. Hunter, and W. mei W. Hwu. CASES, page 79-87. ACM, (2002)Enhancing loop buffering of media and telecommunications applications using low-overhead predication.J. Sias, H. Hunter, and W. mei W. Hwu. MICRO, page 262-273. ACM/IEEE Computer Society, (2001)A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.J. Barth, W. Reohr, P. Parries, G. Fredeman, J. Golz, S. Schuster, R. Matick, H. Hunter, C. Tanner, J. Harig and 7 other author(s). ISSCC, page 486-617. IEEE, (2007)PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research.G. Fursin, T. Moreau, H. Hunter, Y. Chen, C. Qi, and T. Chen. ReQuEST@ASPLOS, page 7. ACM, (2018)Adapting Server Systems for New Memory Technologies.H. Hunter, L. Lastras-Montaño, and B. Bhattacharjee. Computer, 47 (9): 78-84 (2014)Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory.J. Stuecheli, D. Kaseridis, H. Hunter, and L. John. MICRO, page 375-384. IEEE Computer Society, (2010)Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems.J. Mukundan, H. Hunter, K. Kim, J. Stuecheli, and J. Martínez. ISCA, page 48-59. ACM, (2013)The virtual write queue: coordinating DRAM and last-level cache policies.J. Stuecheli, D. Kaseridis, D. Daly, H. Hunter, and L. John. ISCA, page 72-82. ACM, (2010)Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse.D. Connors, H. Hunter, B. Cheng, and W. mei W. Hwu. ASPLOS, page 222-233. ACM Press, (2000)A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.P. Klim, J. Barth, W. Reohr, D. Dick, G. Fredeman, G. Koch, H. Le, A. Khargonekar, P. Wilcox, J. Golz and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)

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Disambiguation of "Hunter, Hillery C."

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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Please choose a person to relate this publication to

Julia Hunter

Hunter Rouse

Charles Hunter

Regina Hunter

Aleksandra Hunter

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hunter, Hillery C."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Please choose a person to relate this publication to

Julia Hunter

Hunter Rouse

Charles Hunter

Regina Hunter

Aleksandra Hunter

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.