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Disambiguation of "Chae, Joo-Hyung"

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A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS.

, , , , , and . ISLPED, page 1-6. IEEE, (2019)

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Hyung-Joo Kim

Hyung-Joo Chi

Hong-Sik Chae

Gyuwon Chae

Yi-Byung Chae

 

Other publications of authors with the same name

Module Implementation and Simulation of Timing Constraint Check Function of I2C Protocol Using Verilog., , and . ICEIC, page 1-4. IEEE, (2023)Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters., , and . IEEE Access, (2022)An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface., , , , , and . ISOCC, page 286-287. IEEE, (2017)A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation., , , , and . ISCAS, page 1-4. IEEE, (2019)A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces., , , , , and . IEEE J. Solid State Circuits, 59 (9): 2971-2982 (September 2024)A 1-Kb 6T 1C XNOR-DRAM Compute-In-Memory Macro With Signed Bit Adder Block for CNN Operations., and . ICEIC, page 1-4. IEEE, (2024)High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line., , , , , , , and . ESSCIRC, page 311-314. IEEE, (2013)A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces., , , , , , and . ISCAS, page 1-5. IEEE, (2021)13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency., , and . ISSCC, page 248-250. IEEE, (2024)A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization., , , , and . IEEE Access, (2018)