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Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , , и . ERSA, стр. 309-310. CSREA Press, (2008)Benchmarks for FPGA-Targeted High-Level-Synthesis., , и . CANDAR, стр. 232-238. IEEE, (2019)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , и . MWSCAS, стр. 1-4. IEEE, (2022)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , и . SoCPaR, стр. 136-140. IEEE, (2015)Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits., , и . ISVLSI, стр. 243-248. IEEE Computer Society, (2004)Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , и . ISMVL, стр. 17. IEEE Computer Society, (2006)Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators., , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2576-2586 (2013)Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors., , , и . IEEE Trans. Circuits Syst. Video Techn., 21 (10): 1453-1466 (2011)Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing., , , и . APCCAS, стр. 639-642. IEEE, (2014)Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages., , и . IEEE Trans. Computers, 54 (6): 642-650 (2005)