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1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Y. Li, K. Kanazawa, T. Izawa, K. Sakui, G. Strof, O. Baumgartner, G. Rzepa, M. Karner, Z. Stanojevic, N. Harada, and F. Masuoka. IMW, page 1-4. IEEE, (2021)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Gerhard Schröck

Risk management and value creation in financial institutionsG. Schröck. Uni Augsburg, (2001)

Johannes Gerhard

Normal vectors for the robust design of dynamical systemsJ. Gerhard. TU Aachen, (2010)

Gerhard Jakob Schmitt-Gerhard

Gerhard Lehmann

Gerhard Rossenbeck

Other publications of authors with the same name

Characterization and physical modeling of the temporal evolution of near-interfacial states resulting from NBTI/PBTI stress in nMOS/pMOS transistors.T. Grasser, B. Stampfer, M. Waltl, G. Rzepa, K. Rupp, F. Schanovsky, G. Pobegen, K. Puschkarsky, H. Reisinger, B. O'Sullivan and 1 other author(s). IRPS, page 2. IEEE, (2018)Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures.J. Michl, A. Grill, D. Claes, G. Rzepa, B. Kaczer, D. Linten, I. Radu, T. Grasser, and M. Waltl. IRPS, page 1-6. IEEE, (2020)Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling.Z. Wu, J. Franco, D. Claes, G. Rzepa, P. Roussel, N. Collaert, G. Groeseneken, D. Linten, T. Grasser, and B. Kaczer. IRPS, page 1-7. IEEE, (2019)Physical modeling of the hysteresis in M0S2 transistors.T. Knobloch, G. Rzepa, Y. Illarionov, M. Waltl, F. Schanovsky, M. Jech, B. Stampfer, M. Furchi, T. Muller, and T. Grasser. ESSDERC, page 284-287. IEEE, (2017)The Mysterious Bipolar Bias Temperature Stress from the Perspective of Gate-Sided Hydrogen Release.T. Grasser, B. Kaczer, B. O'Sullivan, G. Rzepa, B. Stampfer, and M. Waltl. IRPS, page 1-6. IEEE, (2020)Characterization and modeling of charge trapping: From single defects to devices.T. Grasser, G. Rzepa, M. Waltl, W. Goes, K. Rott, G. Rott, H. Reisinger, J. Franco, and B. Kaczer. ICICDT, page 1-4. IEEE, (2014)Comphy - A compact-physics framework for unified modeling of BTI.G. Rzepa, J. Franco, B. O'Sullivan, A. Subirats, M. Simicic, G. Hellings, P. Weckx, M. Jech, T. Knobloch, M. Waltl and 4 other author(s). Microelectron. Reliab., (2018)A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics.F. Schanovsky, D. Verreck, A. Arreghini, G. Rzepa, Z. Stanojevic, C. Kernstock, O. Baumgartner, M. Rosmeulen, and M. Karner. IMW, page 1-4. IEEE, (2021)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.B. O'Sullivan, R. Ritzenthaler, G. Rzepa, Z. Wu, E. Litta, O. Richard, T. Conard, V. Machkaoutsan, P. Fazan, C. Kim and 6 other author(s). IRPS, page 1-8. IEEE, (2019)Characterization and modeling of reliability issues in nanoscale devices.G. Rzepa, W. Goes, B. Kaczer, and T. Grasser. ISCAS, page 2445-2448. IEEE, (2015)

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Disambiguation of "Rzepa, Gerhard"

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DOI
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1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Please choose a person to relate this publication to

Gerhard Schröck

Johannes Gerhard

Gerhard Jakob Schmitt-Gerhard

Gerhard Lehmann

Gerhard Rossenbeck

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Rzepa, Gerhard"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Please choose a person to relate this publication to

Gerhard Schröck

Johannes Gerhard

Gerhard Jakob Schmitt-Gerhard

Gerhard Lehmann

Gerhard Rossenbeck

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.