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ROMA: A Reconfigurable On-chip Memory Architecture for Multi-core Accelerators.

, , , , , , , , , and . HPCC/DSS/SmartCity/DependSys, page 49-57. IEEE, (2023)

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Circuit implementation of floating point range reduction for trigonometric functions., , , , , and . ISCAS, page 3010-3013. IEEE, (2007)Streamline Ring ORAM Accesses through Spatial and Temporal Optimization., , , , , , and . HPCA, page 14-25. IEEE, (2021)Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors., , and . CIT (1), page 86-91. IEEE Computer Society, (2009)Simple and Efficient Heterogeneous Graph Neural Network., , , , and . AAAI, page 10816-10824. AAAI Press, (2023)A High-accurate Multi-objective Exploration Framework for Design Space of CPU., , , , , , , and . DAC, page 1-6. IEEE, (2023)Magma: A Monolithic 3D Vertical Heterogeneous ReRAM-based Main Memory Architecture., , , , and . DAC, page 115. ACM, (2019)On the properties of data migration based on topology pattern keeping on cache hierarchy., , , , and . IGSC, page 1-4. IEEE Computer Society, (2016)Accelerating Sparse Convolutional Neural Networks Based on Dataflow Architecture., , , , , , and . ICA3PP (2), volume 12453 of Lecture Notes in Computer Science, page 14-31. Springer, (2020)CTA: A Critical Task Aware Scheduling Mechanism for Dataflow Architecture., , , , , , and . ICA3PP (1), volume 12452 of Lecture Notes in Computer Science, page 61-77. Springer, (2020)Instruction Vulnerability Test and Code Optimization Against DVFS Attack., , , , , , , and . ITC-Asia, page 49-54. IEEE, (2019)