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High-speed simulator including accurate MTJ models for spintronics integrated circuit design.

, , , , , , , , , , и . ISCAS, стр. 1971-1974. IEEE, (2012)

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Noboru Yamazaki

Noboru Sonoyama

Noboru Hasegawa

Sergio Noboru Kuriyama

 

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A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes., , , , и . IPSJ Trans. Syst. LSI Des. Methodol., (2013)Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode., , , , , и . IEICE Trans. Electron., 90-C (2): 531-535 (2007)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 194-195. IEEE, (2013)MRAM Cell Technology for Over 500-MHz SoC., , , , , , , и . IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , и 5 other автор(ы). ISCAS, стр. 1588-1591. IEEE, (2014)A 90nm 12ns 32Mb 2T1MTJ MRAM., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 462-463. IEEE, (2009)A non-volatile reconfigurable offloader for wireless sensor nodes., , , , и . SIGARCH Comput. Archit. News, 40 (5): 87-92 (2012)Soft-Delay-Error Evaluation in Content-Addressable Memory., , , , , и . ISMVL, стр. 220-225. IEEE Computer Society, (2014)High-speed simulator including accurate MTJ models for spintronics integrated circuit design., , , , , , , , , и 1 other автор(ы). ISCAS, стр. 1971-1974. IEEE, (2012)Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme., , , , , , , и . IEICE Electron. Express, 11 (10): 20140297 (2014)