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Disambiguation of "Ohno, Hideo"

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High-speed simulator including accurate MTJ models for spintronics integrated circuit design.

, , , , , , , , , , and . ISCAS, page 1971-1974. IEEE, (2012)

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Herbert Ohno

Masataka Ohno

Hideo Baba

Terufumi Ohno

Hideo Ohashi

 

Other publications of authors with the same name

Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits., , , , , , , , and . IEICE Trans. Electron., 93-C (5): 608-613 (2010)Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme., , , , , , and . ASP-DAC, page 475-476. IEEE, (2012)Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme., , , , , , , and . IEICE Electron. Express, 11 (10): 20140297 (2014)Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme., , , , and . IEICE Electron. Express, 11 (3): 20131006 (2014)An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (2): 109-119 (2016)10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications., , , , , , , , , and 4 other author(s). ISSCC, page 184-185. IEEE, (2014)A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms., , , , , , , , , and 2 other author(s). CoRR, (2023)Double-Free-Layer Stochastic Magnetic Tunnel Junctions with Synthetic Antiferromagnets., , , , , and . CoRR, (2023)Dependence of Giant Tunnel Magnetoresistance of Sputtered CoFeB/MgO/CoFeB Magnetic Tunnel Junctions on MgO Barrier Thickness and Annealing Temperature, , , , and . Japanese Journal of Applied Physics, 44 (19): 587-589 (2005)