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An analytical timing-driven algorithm for detailed placement.

, , , и . LASCAS, стр. 1-4. IEEE, (2015)

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José Luis Goity

José Luis Morote

José Luis Rivarola

José Luis Narro

Luis José Garcés

 

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Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits., , , , , , и . PATMOS, том 2799 из Lecture Notes in Computer Science, стр. 501-510. Springer, (2003)Improving Critical Path Identification in Functional Timing Analysis., , , и . SBCCI, стр. 297-302. IEEE Computer Society, (2003)Physical design methodologies for performance predictability and manufacturability., , и . Conf. Computing Frontiers, стр. 390-397. ACM, (2004)Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization., , , , и . ICCAD, стр. 528-535. IEEE, (2015)A Transistor Sizing Method Applied to an Automatic Layout Generation Tool., , , , и . SBCCI, стр. 303-. IEEE Computer Society, (2003)A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency., , , и . ISVLSI, стр. 127-132. IEEE Computer Society, (2010)Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective., , и . ICECS, стр. 905-908. IEEE, (2012)Energy-efficient SATD for beyond HEVC., , , и . ISCAS, стр. 802-805. IEEE, (2016)Real-time digital modulation classification based on Support Vector Machines., , , , , и . SBCCI, стр. 1-6. IEEE, (2013)A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool., , , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 732-741. Springer, (2004)