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A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS., , , , , , , , , и 3 other автор(ы). VLSI Circuits, стр. 120-. IEEE, (2019)A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS., , , , , , и . VLSI Circuits, стр. 139-140. IEEE, (2018)Survey on CSI-based Indoor Positioning Systems and Recent Advances., , , , , , , , и . IPIN, стр. 1-8. IEEE, (2019)Atomic Dataflow based Graph-Level Workload Orchestration for Scalable DNN Accelerators., , , , и . HPCA, стр. 475-489. IEEE, (2022)A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications., , , , , , , , , и . IEEE J. Solid State Circuits, 53 (4): 968-982 (2018)AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs., , , , , , , , , и . NVMSA, стр. 1-6. IEEE, (2017)A novel adaptive code block group hybrid automatic repeat request scheme for low earth orbit satellite networks., , , , , и . Int. J. Satell. Commun. Netw., 39 (5): 570-589 (2021)Efficient Scheduling of Irregular Network Structures on CNN Accelerators., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 3408-3419 (2020)An efficient kernel transformation architecture for binary- and ternary-weight neural network inference., , , , и . DAC, стр. 137:1-137:6. ACM, (2018)