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Fast and accurate event-driven simulation of mixed-signal systems with data supplementation., , , and . CICC, page 1-4. IEEE, (2011)22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST., , , , , , , , , and 27 other author(s). ISSCC, page 334-336. IEEE, (2020)A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm., , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2693-2704 (2013)A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , and 29 other author(s). IEEE J. Solid State Circuits, 58 (1): 256-269 (2023)Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits., and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (6): 1381-1394 (2013)True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example., , , and . CICC, page 1-4. IEEE, (2012)A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection., , , and . CICC, page 1-4. IEEE, (2012)A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , and 39 other author(s). ISSCC, page 444-446. IEEE, (2022)A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers., and . ITC, page 1-6. IEEE Computer Society, (2014)A 2.5-V, 160-μJ-output piezoelectric energy harvester and power management IC for batteryless wireless switch (BWS) applications., , , , and . VLSIC, page 282-. IEEE, (2015)