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Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch.

, , , and . IEICE Trans. Inf. Syst., 89-D (3): 1165-1172 (2006)

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Classification of Sequential Circuits Based on tauk Notation and Its Applications., , and . IEICE Trans. Inf. Syst., 88-D (12): 2738-2747 (2005)Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch., , , and . IEICE Trans. Inf. Syst., 89-D (3): 1165-1172 (2006)Sensor deployment strategy for target detection., , , and . WSNA, page 42-48. ACM, (2002)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . ATS, page 409-414. IEEE, (2006)Fault Tolerance in Collaborative Sensor Networks for Target Detection., , and . IEEE Trans. Computers, 53 (3): 320-333 (2004)A Class of Linear Space Compactors for Enhanced Diagnostic., , and . Asian Test Symposium, page 260-265. IEEE Computer Society, (2005)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)Efficient Signature-Based Fault Diagnosis Using Variable Size Windows., , , and . VLSI Design, page 391-396. IEEE Computer Society, (2001)Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation., , and . IEICE Trans. Inf. Syst., 90-D (8): 1202-1212 (2007)Vulnerability of Surveillance Networks to Faults., , , and . IJDSN, 2 (3): 289-311 (2006)