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Routing TCP Flows in Underwater Mesh Networks., , и . IEEE J. Sel. Areas Commun., 29 (10): 2022-2032 (2011)Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools., , , , и . IEICE Trans. Inf. Syst., 91-D (3): 690-699 (2008)Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling., и . J. Electron. Test., 30 (5): 569-580 (2014)An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation., , , , и . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Theory, Analysis and Implementation of an On-Line BIST Technique., и . VLSI Design, 1 (1): 9-22 (1993)Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing., , , , , и . DAC, стр. 527-532. IEEE, (2007)An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults., и . ITC, стр. 675-684. IEEE Computer Society, (1991)Easily Testable Two-Dimensional Cellular Logic Arrays., и . IEEE Trans. Computers, 23 (11): 1204-1207 (1974)Testing Computer Hardware through Data Compression in Space and Time., и . ITC, стр. 83-88. IEEE Computer Society, (1983)Instruction-based delay fault self-testing of pipelined processor cores., , , и . ISCAS (6), стр. 5686-5689. IEEE, (2005)