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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator., , , , , , , , , and 3 other author(s). IEEE Micro, 39 (5): 102-111 (2019)Internal Task-Aware Command Scheduling to Improve Read Performance of Embedded Flash Storage Systems., , , , , , and . IEEE Access, (2021)Hardware and Software Co-optimization for the Initialization Failure of the ReRAM-based Cross-bar Array., , , , and . ACM J. Emerg. Technol. Comput. Syst., 16 (4): 36:1-36:19 (2020)Lightweight Error Correction for In-Storage Acceleration of Large Language Model Inference., , , and . ICEIC, page 1-4. IEEE, (2024)Optimizing Exponent Bias for Sub-8bit Floating-Point Inference of Fine-tuned Transformers., and . AICAS, page 98-101. IEEE, (2022)Supporting handover in an IEEE 802.11p-based wireless access system., and . Vehicular Ad Hoc Networks, page 75-80. ACM, (2010)A Time Synchronization Protocol for Barrage Relay Networks., , , , and . Sensors, 23 (5): 2447 (March 2023)PillarAcc: Sparse PointPillars Accelerator for Real-Time Point Cloud 3D Object Detection on Edge Devices., , , , , , , and . CoRR, (2023)Robust Machine Learning Systems: Challenges, Current Trends, Perspectives, and the Road Ahead., , , , , , and . CoRR, (2021)