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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling., , , , , , , , , и 34 other автор(ы). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator., , , , , , , , , и 3 other автор(ы). IEEE Micro, 39 (5): 102-111 (2019)4-Bit Quantization of LSTM-Based Speech Recognition Models., , , , , , , , , и 2 other автор(ы). Interspeech, стр. 2586-2590. ISCA, (2021)Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators., , , и . ISPASS, стр. 240-242. IEEE, (2021)ScaleCom: Scalable Sparsified Gradient Compression for Communication-Efficient Distributed Training., , , , , , , , , и 1 other автор(ы). NeurIPS, (2020)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference., , , , , , , , , и 44 other автор(ы). ISCA, стр. 153-166. IEEE, (2021)A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel., , , , , , , , и . COOL CHIPS, стр. 1-3. IEEE, (2019)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference., , , , , , , , , и 33 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS., , , , , , , , , и 6 other автор(ы). VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)Exploiting approximate computing for deep learning acceleration., , , , и . DATE, стр. 821-826. IEEE, (2018)